Latched Differential Fet Logic

In this paper, we propose a new circuit topology for creating complex logic circuits in GaAs. Latched Differential FET Logic (LDFL) is a fully differential logic family that provides complex logic function capability, tolerance to threshold voltage variations and complementary, latched-function outputs. LDFL is capable of performing up to eleven levels of logic in one gate, while still giving excellent performance. LDFL also provides improved noise margins due to the use of bootstrapped loads and significantly reduces the load-blogic ratioing constraint. A nine-level LDFL gate has a delay of 1.7ns and a static power dissipation of 4mW as demonstrated in simulations of Cbit digital comparator circuits. INTRODUCTION GaAs MESFET circuit technology provides a means of creating high-speed digital logic circuits. One common problem with standard GaAs logic families such as Buffered FET Logic (BFL), Direct-Coupled FET Logic (DCFL) and Schottky-Diode FET Logic (SDFL) is the inability t o perform complex logic functions in a single gate. While dynamic Domino Logic [l] provides the ability to perform complex functions, designs are more critical and require complex clockhg. As well, domino logic does not provide complementary output signals; hence it cannot be used t o implement some logic functions such as comparators and XOR gates. The differential FET logic style proposed here is motivated by CMOS CVSL [2] and is similar in principle t o Enabled/disabled CMOS Differential Logic (ECDL) [3]. Latched Differential FET Logic (LDFL) is capable of implementing complex logic functions with a single differential tree network. Designs are stable and easy to margin. Since both polarities of the result are available, LDFL increases logic flexiblity without ext ra circuitry. As well, its differential logic style provides tolerance t o threshold-voltage variations, which is crucial in current GaAs technologies. LDFL has applications in the area of high speed ALUs, iterative networks [3] and random combinational circuits. Simulations in a l p m GaAs E/D process show LDFL is capable of supporting up t o eleven series FETs in its logic trees l . The latched outputs are stable and have good noise margins . The proposed LDFL circuit is described in detail in the following sections. Section I1 describes the topology and operation of DFL. Section I11 summarizes simulation results and, finally, section IV presents conclusions. 'This number is process dependent. Figure 1. The LDFL Circuit Topology. Table 1. LDFL Logic Levels and Power Supplies TOPOLOGY AND OPERATION Topology:-The topology of a LDFL circuit is shown in figure 1. A gate consists of a differential logic tree that implements the desired function, a cross-coupled amplifier to amplify and latch the imbalance created by the logic tree, and two BFL inverters for buffering and level shifting. The logic levels used externally in LDFL are shown in table l. These levels were chosen so that DFETs may be used in the logic tree, and to provide a larger input noise margin. Internally, DCFL levels are used in the cross-coupled amplifier. LDFL requires the use of three power supplies as shown in table 1. Ci rcu i t Operation:-An example of an LDFL circuit is shown in figure 2. The circuit operates by utilizing a differential imbalance created on the latch output nodes t o flip the state of the DCFL cross-coupled latch. Thus in order to switch, one CH 3W/91/0000 301 1 $1.00 0 EEE